SH7206 Datasheet, PDF (214/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Cache
7.3.2 Read Access
(1) Read Hit
In a read access, data is transferred from the cache to the CPU. LRU is updated so that the hit way
is the latest.
(2) Read Miss
An external bus cycle starts and the entry is updated. The way replaced follows table 7.4. Entries
are updated in 16-byte units. When the desired data that caused the miss is loaded from external
memory to the cache, the data is transferred to the CPU in parallel with being loaded to the cache.
When it is loaded in the cache, the V bit is set to 1, and LRU is updated so that the replaced way
becomes the latest. In operand cache, the U bit is additionally cleared to 0. When the U bit of the
entry to be replaced by updating the entry in write-back mode is 1, the cache update cycle starts
after the entry is transferred to the write-back buffer. After the cache completes its update cycle,
the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes. The
update of cache and write-back to memory are performed in wrap around method. For example,
the lower four bits of the address at which a read miss occurs indicate H'4, the update of cache and
write-back to memory are performed in the order of H'4, H'8, H'C, H'0, which are the lower four
bits of the address.
7.3.3 Prefetch Operation (Only for Operand Cache)
(1) Prefetch Hit
LRU is updated so that the hit way becomes the latest. The contents in other caches are not
modified. No data is transferred to the CPU.
(2) Prefetch Miss
No data is transferred to the CPU. The way to be replaced follows table 7.3. Other operations are
the same in case of read miss.
Rev. 3.00 Jun. 18, 2008 Page 190 of 1160
REJ09B0191-0300