SH7206 Datasheet, PDF (747/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

WTCNT
value
H'FF
Section 14 Watchdog Timer (WDT)
Overflow
H'00
WT/IT = 1
TME = 1
WDTOVF
signal
H'00 written
in WTCNT
WOVF = 1
WT/IT = 1
TME = 1
WDTOVF and internal reset generated
H'00 written
in WTCNT
Time
Internal
reset signal*
64 × Pφ clock cycles
128 × Pφ clock cycles
[Legend]
WT/IT: Timer mode select bit
TME: Timer enable bit
Note: * Internal reset signal occurs only when the RSTE bit is set to 1.
Figure 14.4 Operation in Watchdog Timer Mode
Rev. 3.00 Jun. 18, 2008 Page 723 of 1160
REJ09B0191-0300