SH7206 Datasheet, PDF (1161/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Main Revisions and Additions in This Edition
Item
1.1 SH7206 Features
Table 1.1 SH7206 Features
1.4 Pin Functions
Table 1.2 Pin Functions
2.1.3 System Registers
(3) Program Counter (PC)
3.2 Input/Output Pins
Table 3.1 Pin Configuration and
Functions of the Clock Pulse
Generator
Page Revision (See Manual for Details)
3
Specification of Cache memory amended.
• 128-entry/way, 4-way set associative, 16-byte block
length configuration each for the instruction cache
and operand cache
• Way lock function available (only for operand
cache); ways 2 and 3 can be locked
5
Specification of Multi-function timer pulse unit 2 (MTU2)
amended.
• Pulse output modes
One shot, Toggle, PWM, complementary PWM, and
reset-synchronized PWM modes
10 _{Table amended.}
Classification Symbol I/O
Operating mode ASEMD I
control
Name
ASE mode
Fuction
If a low level is input at the ASEMD
pin while the RES pin is asserted,
ASE mode is entered; if a high level i
s input, product chip mode is
entered.
In ASE mode, the emulator function
is enabled. When this function is not
in use, fix it high.
32 Description amended.
PC points four bytes ahead of the current instruction
and controls the flow of the processing.
32 Description amended.
PC points four bytes ahead of the instruction being
executed.
73 Function (Clock Operating Mode 7) of Crystal
input/output pins (clock input pins) amended.
(Before) Pull up this pin. →
(After) Fix (pull up/pull down/connect to power
supply/connect to ground) this pin.
Rev. 3.00 Jun. 18, 2008 Page 1137 of 1160
REJ09B0191-0300