SH7206 Datasheet, PDF (782/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
3
MCE
0
R/W Modem Control Enable
Enables modem control signals CTS and RTS.
For channels 0 to 2 in clocked synchronous mode, MCE
bit should always be 0.
0: Modem signal disabled*
1: Modem signal enabled
Note: * Regardless of the input value, CTS level and
RTS level have no effect on the transmit
operation and the receive operation.
2
TFRST
0
R/W Transmit FIFO Data Register Reset
Disables the transmit data in the transmit FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
1
RFRST
0
R/W Receive FIFO Data Register Reset
Disables the receive data in the receive FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
0
LOOP
0
R/W Loop-Back Test
Internally connects the transmit output pin (TxD) and
receive input pin (RxD) and internally connects the RTS
pin and CTS pin and enables loop-back testing.
0: Loop back test disabled
1: Loop back test enabled
Rev. 3.00 Jun. 18, 2008 Page 758 of 1160
REJ09B0191-0300