SH7206 Datasheet, PDF (412/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Direct Memory Access Controller (DMAC)
Table 9.6 Selecting External Request Detection with DL and DS Bits
DL bit
0
1
CHCR
DS bit
0
1
0
1
Detection of External Request
Low level detection
Falling edge detection
High level detection
Rising edge detection
When DREQ is accepted, the DREQ pin enters the request accept disabled state (non-sensitive
period). After issuing acknowledge DACK signal for the accepted DREQ, the DREQ pin again
enters the request accept enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
Overrun 0: Transfer is terminated after the same number of transfer has been performed as
requests.
Overrun 1: Transfer is terminated after transfers have been performed for (the number of requests
plus 1) times.
The DO bit in CHCR selects this overrun 0 or overrun 1.
Table 9.7 Selecting External Request Detection with DO Bit
CHCR
DO bit
0
1
External Request
Overrun 0
Overrun 1
Rev. 3.00 Jun. 18, 2008 Page 388 of 1160
REJ09B0191-0300