SH7206 Datasheet, PDF (408/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Direct Memory Access Controller (DMAC)
Table 9.4 DMARS Settings
Peripheral Module
SCIF_0
SCIF_1
SCIF_2
SCIF_3
IIC3
A/D converter_0
A/D converter_1
MTU2_0
MTU2_1
MTU2_2
MTU2_3
MTU2_4
CMT_0
CMT_1
Setting Value for One
Channel ({MID, RID})
H'81
H'82
H'85
H'86
H'89
H'8A
H'8D
H'8E
H'A1
H'A2
H'B3
H'B7
H'E3
H'E7
H'EB
H'EF
H'F3
H'FB
H'FF
MID
B'100000
B'100001
B'100010
B'100011
B'101000
B'101100
B'101101
B'111000
B'111001
B'111010
B'111011
B'111100
B'111110
B'111111
RID
B'01
B'10
B'01
B'10
B'01
B'10
B'01
B'10
B'01
B'10
B'11
B'11
B'11
B'11
B'11
B'11
B'11
B'11
B'11
Function
Transmit
Receive
Transmit
Receive
Transmit
Receive
Transmit
Receive
Transmit
Receive









When MID or RID other than the values listed in table 9.4 is set, the operation of this LSI is not
guaranteed. The transfer request from DMARS is valid only when the resource select bits
(RS[3:0]) in CHCR0 to CHCR7 have been set to B'1000. Otherwise, even if DMARS has been set,
the transfer request source is not accepted.
Rev. 3.00 Jun. 18, 2008 Page 384 of 1160
REJ09B0191-0300