SH7206 Datasheet, PDF (234/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
3, 2

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
HIZMEM 0
R/W High-Z Memory Control
Specifies the pin state in software standby mode for
A25 to A0, BS, CSn, CS2x, RD/WR, WEn/DQMxx/AH,
RD, and FRAME. At bus-released state, these pin are
high-impedance states regardless of the setting value
of the HIZMEM bit.
0: High impedance in software standby mode.
1: Driven in software standby mode
0
HIZCNT
0
R/W High-Z Control
Specifies the state in software standby mode and bus-
released state for CKIO, CKE, RASU, RASL, CASU,
and CASL.
0: High impedance in software standby mode and bus-
released state for CKIO, CKE, RASU, RASL, CASU,
and CASL.
1: Driven in software standby mode and bus-released
state for CKIO, CKE, RASU, RASL, CASU, and
CASL.
Rev. 3.00 Jun. 18, 2008 Page 210 of 1160
REJ09B0191-0300