SH7206 Datasheet, PDF (774/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.3 SCSMR Settings
n
Clock Source
CKS[1]
0
Pφ
0
1
Pφ/4
0
2
Pφ/16
1
3
Pφ/64
1
SCSMR Settings
CKS[0]
0
1
0
1
The bit rate error in asynchronous is given by the following formula:
Error (%) =
Pφ × 10⁶
− 1 × 100
(N + 1) × B × 64 × 2^2n-1
Table 15.4 lists examples of SCBRR settings in asynchronous mode, and table 15.5 lists examples
of SCBRR settings in clocked synchronous mode.
Table 15.4 Bit Rates and SCBRR Settings (Asynchronous Mode)
Bit Rate (bit/s) n
110
2
150
2
300
1
600
1
1200
0
2400
0
4800
0
9600
0
19200
0
31250
0
38400
0
5
N
Error (%) n
88
−0.25
2
64
0.16
2
129 0.16
1
64
0.16
1
129 0.16
0
64
0.16
0
32
−1.36
0
15
1.73
0
7
1.73
0
4
0.00
0
3
1.73
0
Pφ (MHz)
6
N
Error (%) n
106 −0.44 2
77
0.16
2
155 0.16
1
77
0.16
1
155 0.16
0
77
0.16
0
38
0.16
0
19
−2.34 0
9
−2.34 0
5
0.00
0
4
−2.34 0
6.144
N
Error (%)
108 0.08
79 0.00
159 0.00
79 0.00
159 0.00
79 0.00
39 0.00
19 0.00
9
0.00
5
2.40
4
0.00
Rev. 3.00 Jun. 18, 2008 Page 750 of 1160
REJ09B0191-0300