SH7206 Datasheet, PDF (702/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Port Output Enable 2 (POE2)
Initial
Bit
Bit Name Value R/W Description
7 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
12.3.3 Input Level Control/Status Register 2 (ICSR2)
ICSR2 is a 16-bit readable/writable register that selects the POE4 to POE7 pin input modes,
controls the enable/disable of interrupts, and indicates status.
Bit: 15 14 13 12 11 10
POE7F POE6F POE5F POE4F -
-
Initial value: 0
0
0
0
0
0
R/W: R/(W)*¹R/(W)*¹R/(W)*¹ R/(W)*¹ R
R
9
8
7
6
5
4
3
2
1
0
- PIE2 POE7M[1:0] POE6M[1:0] POE5M[1:0] POE4M[1:0]
0
0
0
0
0
0
0
0
0
0
R R/W R/W*² R/W*² R/W*² R/W*² R/W*² R/W*² R/W*² R/W*²
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
Initial
Bit Bit Name Value R/W Description
15
POE7F 0
R/(W)*¹ POE7 Flag
Indicates that a high impedance request has been input
to the POE7 pin.
[Clearing conditions]
• By writing 0 to POE7F after reading POE7F = 1
(when the falling edge is selected by bits 7 and 6 in
ICSR2)
• By writing 0 to POE7F after reading POE7F = 1 after
a high level input to POE7 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 7 and 6 in ICSR2)
[Setting condition]
• When the input condition set by bits 7 and 6 in ICSR2
occurs at the POE7 pin
Rev. 3.00 Jun. 18, 2008 Page 678 of 1160
REJ09B0191-0300