SH7206 Datasheet, PDF (1172/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Item
17.7.7 Note on Usage in Scan
Mode and Multi Mode
19.3.2 Port F
Table 19.15 Switching Pin
Function of PF6/AN6/DA0 and
PF7/AN7/DA1
20.1 Features
20.6 Port E
Figure 20.5 Port E
22.3.2 Software Standby Mode
(3) Note on Release from
Software Standby Mode
22.4.1 Note on Writing to
Registers
23.5 Usage Notes
24.2 Register Bits
Page Revision (See Manual for Details)
861 Added.
943 Table replaced.
945 Description amended.
2. The following pins in this LSI have weak keeper
circuits that prevent the pins from floating into
intermediate voltage levels.
… If the pull-up or pull-down resistors become
necessary to fix the pin level, use the resistor of 10 kΩ
or smaller.
966 Figure amended.
992 Added.
PE13 (I/O) / TIOC4B (I/O) / MRES (input)
PE12 (I/O) / TIOC4A (I/O) / TxD3 (output)
PE11 (I/O) / TIOC3D (I/O) / RxD3 (input) / CTS3 (I/O)
995 Title added.
1004 Description amended.
4. When the TDO change timing switch command is set
and the TRST pin is asserted immediately after and
the RES pin is negated, the TDO change timing
switch command may be cleared. To prevent this,
make sure to put 20 t or more between the signal
cyc
change timing of the RES and TRST pins when the
TDO change timing switch command is set.
For details, see section 23.4.3, TDO Output Timing.
1025 Bit 20 of CS0WCR in BSC amended.
(Before) BAS → (After) 
1040 Bit 0 of TOCR1S in MTU2S amended.
(Before) PLSP → (After) OLSP
Rev. 3.00 Jun. 18, 2008 Page 1148 of 1160
REJ09B0191-0300