SH7206 Datasheet, PDF (880/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 A/D Converter (ADC)
17.5 Interrupt Sources and DMAC Transfer Request
The A/D converter generates an A/D conversion end interrupt (ADI0 or ADI1) at the end of A/D
conversion. An ADI0 or ADI1 interrupt request is generated if the ADIE bit is set to 1 when the
ADF bit in ADCSR is set to 1 on completion of A/D conversion. Note that the direct memory
access controller (DMAC) can be activated by an ADI interrupt depending on the DMAC setting.
In this case, an interrupt is not issued to the CPU. If the setting to activate the DMAC has not been
made, an interrupt request is sent to the CPU. Having the converted data read by the DMAC in
response to an ADI interrupt enables continuous conversion to be achieved without imposing a
load on software.
In single mode, set the DMAC so that DMA transfer initiated by an ADI interrupt is performed
only once. In the case of A/D conversion on multiple channels in scan mode or multi mode, setting
the DMA transfer count to one causes DMA transfer to finish after transferring only one channel
of data. To make the DMAC transfer all conversion data, set the ADDR where A/D conversion
data is stored as the transfer source address, and the number of converted channels as the transfer
count (set the TC bit of the DMA channel control register (CHCR) in the DMAC to 1 and set the
number of converted channels in the DMA transfer count register (DMATCR)).
When the DMAC is activated by ADI0 or ADI1, the ADF bit in ADCSR is automatically cleared
to 0 when data is transferred by the DMAC.
Table 17.6 Relationship between Interrupt Sources and DMAC Transfer Request
Name
ADI0
ADI1
Interrupt Source
A/D conversion end
A/D conversion end
Interrupt Flag
ADF in ADCSR_0
ADF in ADCSR_1
DMAC Activation
Possible
Possible
Rev. 3.00 Jun. 18, 2008 Page 856 of 1160
REJ09B0191-0300