SH7206 Datasheet, PDF (1101/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 Electrical Characteristics
25.4.2 Control Signal Timing
Table 25.7 Control Signal Timing
Conditions: PV_CC = 3.0 V to 3.6 V, V_CC = 1.15 V to 1.35 V, AV_CC = 3.0 V to 3.6 V,
PV_SS = V_SS = AV_SS = 0 V, Ta = −20°C to +85°C
Bφ = 66.67 MHz
Item
Symbol Min.
Max.
Unit Figure
RES pulse width
MRES pulse width
NMI pulse width
IRQ pulse width
t_RESW
20*¹
—
t_MRESW
20*²
—
t_NMIW
20*³
—
t_IRQW
20*³
—
t_cyc
Figure 25.8
t_cyc
t_cyc
Figure 25.9
t_cyc
PINT pulse width
IRQOUT/REFOUT output delay time
BREQ setup time
BREQ hold time
BACK delay time
t_PINTW
t_IRQOD
t_BREQS
t_BREQH
t_BACKD
20
—
1/2t_cyc + 7
1/2t_cyc + 2
—
—
t_cyc
100
ns
—
ns
—
ns
1/2t_cyc + 13 ns
Figure 25.10
Figure 25.11
Bus buffer off time 1
t_BOFF1
—
15
ns
Bus buffer off time 2
t_BOFF2
—
15
ns
Bus buffer on time 1
t_BON1
—
15
ns
Bus buffer on time 2
t_BON2
—
BACK setup time for bus buffer off
t_BACKS
0
15
ns
—
ns
Notes: 1. In standby mode or when the clock multiplication ratio is changed, t = t (10 ms).
RESW
OSC2
2. In standby mode, t_MRESW = t_OSC2 (10 ms).
3. In standby mode, t /t = t (10 ms).
NMIW IRQW
OSC2
Rev. 3.00 Jun. 18, 2008 Page 1077 of 1160
REJ09B0191-0300