SH7206 Datasheet, PDF (207/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Cache
Bit
Bit Name
31 to 12 
11
ICF
10, 9 
8
ICE
7 to 4 
3
OCF
2

1
WT
0
OCE
Initial
Value
All 0
0
All 0
0
All 0
0
0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Instruction Cache Flush
Writing 1 flushes all instruction cache entries (clears the
V and LRU bits of all instruction cache entries to 0).
Always reads 0. Write-back to external memory is not
performed when the instruction cache is flushed.
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Instruction Cache Enable
Indicates whether the instruction cache function is
enabled/disabled.
0: Instruction cache disable
1: Instruction cache enable
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Operand Cache Flush
Writing 1 flushes all operand cache entries (clears the
V, U, and LRU bits of all operand cache entries to 0).
Always reads 0. Write-back to external memory is not
performed when the operand cache is flushed.
R Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Write Through
Selects write-back mode or write-through mode.
0: Write-back mode
1: Write-through mode
R/W Operand Cache Enable
Indicates whether the operand cache function is
enabled/disabled.
0: Operand cache disable
1: Operand cache enable
Rev. 3.00 Jun. 18, 2008 Page 183 of 1160
REJ09B0191-0300