SH7206 Datasheet, PDF (488/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)
The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring
data from the buffer register to the timer general register in PWM mode. The MTU2 has three
TBTM registers, one each for channels 0, 3, and 4.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
- TTSE TTSB TTSA
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W
Bit
Bit Name
7 to 3 —
2
TTSE
1
TTSB
0
TTSA
Initial
Value
All 0
0
0
0
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Timing Select E
Specifies the timing for transferring data from TGRF_0
to TGRE_0 when they are used together for buffer
operation.
In channels 3 and 4, bit 2 is reserved. It is always read
as 0 and the write value should always be 0.
0: When compare match E occurs in channel 0
1: When TCNT_0 is cleared
Timing Select B
Specifies the timing for transferring data from TGRD to
TGRB in each channel when they are used together for
buffer operation.
0: When compare match B occurs in each channel
1: When TCNT is cleared in each channel
Timing Select A
Specifies the timing for transferring data from TGRC to
TGRA in each channel when they are used together for
buffer operation.
0: When compare match A occurs in each channel
1: When TCNT is cleared in each channel
Rev. 3.00 Jun. 18, 2008 Page 464 of 1160
REJ09B0191-0300