SH7206 Datasheet, PDF (648/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.7.17 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 10.133 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
MPφ
TCNT input
clock
TCNT
Counter clear
signal
TGF
TCFV
H'FFFF
Disabled
H'0000
Figure 10.133 Contention between Overflow and Counter Clearing
Rev. 3.00 Jun. 18, 2008 Page 624 of 1160
REJ09B0191-0300