SH7206 Datasheet, PDF (1179/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Global base register (GBR) ...................... 31
H
High-performance user debugging
interface (H-UDI) ................................... 997
H-UDI commands................................. 1000
H-UDI interrupt ............................ 127, 1003
H-UDI related pin timing...................... 1123
H-UDI reset .......................................... 1003
I
I/O port timing ...................................... 1122
I/O ports.................................................. 945
I²C bus format......................................... 810
I²C bus interface 3 (IIC3) ....................... 791
IIC3 module timing .............................. 1120
Immediate data ......................................... 38
Immediate data accessing ......................... 38
Immediate data format.............................. 35
Initial values of control registers .............. 33
Initial values of general registers .............. 33
Initial values of system registers............... 33
Instruction features ................................... 36
Instruction format ..................................... 45
Instruction set ........................................... 49
Integer division exceptions ..................... 105
Interrupt controller (INTC)..................... 111
Interrupt exception handling................... 102
Interrupt exception handling vectors
and priorities ........................................... 131
Interrupt priority level............................. 101
Interrupt response time ........................... 143
IRQ interrupts ......................................... 128
J
Jump table base register (TBR) ................ 31
L
Load-store architecture ............................. 36
Logic operation instructions...................... 61
Low-frequency mode .............................. 315
Low-power SDRAM............................... 320
LRU ........................................................ 181
M
Manual reset.............................................. 96
Master receive operation......................... 813
Master transmit operation ....................... 811
Memory-mapped cache........................... 194
Module standby function ........................ 994
MPX-I/O interface .................................. 275
MTU2 functions...................................... 414
MTU2 interrupts ..................................... 595
MTU2 output pin initialization ............... 627
MTU2, MTU2S module timing ............ 1117
MTU2–MTU2S synchronous
operation ................................................. 583
MTU2S functions.................................... 660
Multi mode.............................................. 848
Multi-function timer pulse unit 2
(MTU2)................................................... 413
Multi-function timer pulse unit 2S
(MTU2S)................................................. 659
Multiplexed pins (port A) ....................... 871
Multiplexed pins (port B)........................ 872
Multiplexed pins (port C)........................ 872
Multiplexed pins (port D) ....................... 873
Multiplexed pins (port E)........................ 874
Multiplexed pins (port F) ........................ 875
Multiply and accumulate register high
(MACH).................................................... 32
Multiply and accumulate register low
(MACL) .................................................... 32
Multiply/Multiply-and-accumulate
operations.................................................. 37
Rev. 3.00 Jun. 18, 2008 Page 1155 of 1160
REJ09B0191-0300