SH7206 Datasheet, PDF (470/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 10.25 TIORL_3 (Channel 3)
Description
Bit 3 Bit 2 Bit 1 Bit 0 TGRC_3
IOC3 IOC2 IOC1 IOC0 Function
TIOC3C Pin Function
0
0
0
0
Output
Output retained*¹
1
compare
register*²
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
X
0
0
Input capture Input capture at rising edge
1
register*²
Input capture at falling edge
1
X
Input capture at both edges
[Legend]
X:
Don't care
Notes: 1. After power-on reset, 0 is output until TIOR is set.
2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 3.00 Jun. 18, 2008 Page 446 of 1160
REJ09B0191-0300