SH7206 Datasheet, PDF (96/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 3 Clock Pulse Generator (CPG)
(7) Standby Control Circuit
The standby control circuit controls the states of the clock pulse generator and other modules
during clock switching, or sleep or software standby mode.
(8) Frequency Control Register (FRQCR)
The frequency control register (FRQCR) has control bits assigned for the following functions:
clock output/non-output from the CKIO pin during software standby mode, the frequency
multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the
peripheral clock (Pφ).
(9) MTU Clock Frequency Control Register (MCLKCR)
The MTU clock frequency control register (MCLKCR) has control bits assigned for the following
functions: MTU clock output/non-output and the frequency division ratio.
(10) Standby Control Register
The standby control register has bits for controlling the power-down modes. See section 22,
Power-Down Modes, for more information.
Rev. 3.00 Jun. 18, 2008 Page 72 of 1160
REJ09B0191-0300