SH7206 Datasheet, PDF (339/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
(10) Low-Frequency Mode
When the SLOW bit in SDCR is set to 1, output of commands, addresses, and write data, and
fetch of read data are performed at a timing suitable for operating SDRAM at a low frequency.
Figure 8.31 shows the access timing in low-frequency mode. In this mode, commands, addresses,
and write data are output in synchronization with the falling edge of CKIO, which is half a cycle
delayed than the normal timing. Read data is fetched at the rising edge of CKIO, which is half a
cycle faster than the normal timing. This timing allows the hold time of commands, addresses,
write data, and read data to be extended.
If SDRAM is operated at a high frequency with the SLOW bit set to 1, the setup time of
commands, addresses, write data, and read data are not guaranteed. Take the operating frequency
and timing design into consideration when making the SLOW bit setting.
CKIO
CKE
Tr
Tc1 Td1
Tde
Tap
Tr
Tc1 Tnop Trwl
Tap
(High)
A25 to A0
A12/A11*¹
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 8.31 Low-Frequency Mode Access Timing
Rev. 3.00 Jun. 18, 2008 Page 315 of 1160
REJ09B0191-0300