SH7206 Datasheet, PDF (347/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
8.5.7 Burst ROM (Clocked Asynchronous) Interface
The burst ROM (clocked asynchronous) interface is used to access a memory with a high-speed
read function using a method of address switching called the burst mode or page mode. In a burst
ROM (clocked asynchronous) interface, basically the same access as the normal space is
performed, but the 2nd and subsequent access cycles are performed only by changing the address,
without negating the RD signal at the end of the 1st cycle. In the 2nd and subsequent access
cycles, addresses are changed at the falling edge of the CKIO.
For the 1st access cycle, the number of wait cycles specified by the W3 to W0 bits in CSnWCR is
inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the W1
to W0 bits in CSnWCR is inserted.
In the access to the burst ROM (clocked asynchronous), the BS signal is asserted only to the first
access cycle. An external wait input is valid only to the first access cycle.
In the single access or write access that does not perform the burst operation in the burst ROM
(clocked asynchronous) interface, access timing is same as a normal space. In addition, there are
some restrictions on 16-byte write access. For details, see section 8.6, Usage Notes.
Table 8.17 lists a relationship between bus width, access size, and the number of bursts. Figure
8.36 shows a timing chart.
Table 8.17 Relationship between Bus Width, Access Size, and Number of Bursts
Bus Width
8 bits
Access Size
8 bits
16 bits
32 bits
16 bytes
16 bits
8 bits
16 bits
32 bits
16 bytes
CSnWCR. BST[1:0] Bits Number of Bursts Access Count
Not affected
1
1
Not affected
2
1
Not affected
4
1
00
16
1
01
4
4
Not affected
1
1
Not affected
1
1
Not affected
2
1
00
8
1
01
2
4
10*
4
2
2, 4, 2
3
Rev. 3.00 Jun. 18, 2008 Page 323 of 1160
REJ09B0191-0300