SH7206 Datasheet, PDF (18/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 14 Watchdog Timer (WDT) ................................................................. 711
14.1 Features.............................................................................................................................. 711
14.2 Input/Output Pin ................................................................................................................ 713
14.3 Register Descriptions......................................................................................................... 714
14.3.1 Watchdog Timer Counter (WTCNT).................................................................... 714
14.3.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 715
14.3.3 Watchdog Reset Control/Status Register (WRCSR) ............................................ 717
14.3.4 Notes on Register Access ..................................................................................... 718
14.4 WDT Usage ....................................................................................................................... 720
14.4.1 Canceling Software Standby Mode ...................................................................... 720
14.4.2 Changing the Frequency ....................................................................................... 721
14.4.3 Using Watchdog Timer Mode .............................................................................. 722
14.4.4 Using Interval Timer Mode .................................................................................. 724
14.5 Usage Notes ....................................................................................................................... 725
14.5.1 Timer Variation .................................................................................................... 725
14.5.2 Prohibition against Setting H'FF to WTCNT........................................................ 725
14.5.3 Interval Timer Overflow Flag............................................................................... 725
14.5.4 System Reset by WDTOVF Signal....................................................................... 726
14.5.5 Manual Reset in Watchdog Timer Mode.............................................................. 726
Section 15 Serial Communication Interface with FIFO (SCIF)........................ 727
15.1 Features.............................................................................................................................. 727
15.2 Input/Output Pins............................................................................................................... 729
15.3 Register Descriptions......................................................................................................... 730
15.3.1 Receive Shift Register (SCRSR) .......................................................................... 732
15.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 732
15.3.3 Transmit Shift Register (SCTSR) ......................................................................... 733
15.3.4 Transmit FIFO Data Register (SCFTDR)............................................................. 733
15.3.5 Serial Mode Register (SCSMR)............................................................................ 734
15.3.6 Serial Control Register (SCSCR).......................................................................... 737
15.3.7 Serial Status Register (SCFSR) ............................................................................ 741
15.3.8 Bit Rate Register (SCBRR) .................................................................................. 749
15.3.9 FIFO Control Register (SCFCR) .......................................................................... 756
15.3.10 FIFO Data Count Set Register (SCFDR).............................................................. 759
15.3.11 Serial Port Register (SCSPTR) ............................................................................. 760
15.3.12 Line Status Register (SCLSR) .............................................................................. 762
15.4 Operation ........................................................................................................................... 764
15.4.1 Overview .............................................................................................................. 764
15.4.2 Operation in Asynchronous Mode ........................................................................ 766
15.4.3 Operation in Clocked Synchronous Mode ............................................................ 777
Rev. 3.00 Jun. 18, 2008 Page xviii of xxiv