SH7206 Datasheet, PDF (27/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
Items
Cache memory
Interrupt controller
(INTC)
Bus state controller
(BSC)
Specification
• Instruction cache: 8 Kbytes
• Operand cache: 8 Kbytes
• 128-entry/way, 4-way set associative, 16-byte block length
configuration each for the instruction cache and operand cache
• Write-back, write-through, LRU replacement algorithm
• Way lock function available (only for operand cache); ways 2 and 3
can be locked
• Seventeen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT7 to
PINT0)
• On-chip peripheral interrupts: Priority level set for each module
• 16 priority levels available
• Register bank enabling fast register saving and restoring in interrupt
processing
• Address space divided into nine areas (0 to 8), each a maximum of 64
Mbytes
• The following features settable for each area independently
 Bus size (8, 16, or 32 bits): Available sizes depend on the area.
 Number of access wait cycles (different wait cycles can be
specified for read and write access cycles in some areas)
 Idle wait cycle insertion (between same area access cycles or
different area access cycles)
 Specifying the memory to be connected to each area enables
direct connection to SRAM, SRAM with byte selection, SDRAM,
and burst ROM (clocked synchronous or asynchronous). The
address/data multiplexed I/O (MPX) interface and burst MPX-I/O
interface are also available.
 PCMCIA interface
 Outputs a chip select signal (CS0 to CS8) according to the target
area (CS assert or negate timing can be selected by software)
• SDRAM refresh
Auto refresh or self refresh mode selectable
• SDRAM burst access
Rev. 3.00 Jun. 18, 2008 Page 3 of 1160
REJ09B0191-0300