SH7206 Datasheet, PDF (1170/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Item
Page Revision (See Manual for Details)
15.4.3 Operation in Clocked
780 Figure amended.
Synchronous Mode
(3) Transmitting and Receiving
Data
Figure 15.13 Sample Flowchart for
Transmitting Serial Data
Start of transmission
Read TDFE flag in SCFSR
No
TDFE = 1?
[1] SCIF status check and transmit data
write:
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR, and clear
the TDFE and TEND flags to 0 after
Yes
Write transmit data to SCFTDR
and clear TDFE and TEND flags
[1]
in SCFSR to 0 after reading 1
No
All data transmitted?
reading 1.
[2] Serial transmission continuation
procedeure:
To continue serial transmission, read
1 from the TDFE flag to confirm that
writing is possible, then write data to
SCFTDR, and then clear the TDFE
Yes
[2]
15.4.3 Operation in Clocked
785
Synchronous Mode
(3) Transmitting and Receiving
Data
Figure 15.18 Sample Flowchart for
Transmitting/Receiving Serial
Data
Figure amended.
Initialization
Start of transmission and reception
Read TDFE flag in SCFSR
No
TDFE = 1?
Yes
Write transmit data to SCFTDR,
and clear TDFE and TEND flags ^[1]
in SCFSR to 0 after reading 1
[1] SCIF status check and transmit data
write:
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR, and clear
the TDFE and TEND flags to 0 after
reading 1. The transition of the TDFE
flag from 0 to 1 can also be identified
by a transmit FIFO data empty
interrupt (TXI).
[2] Receive error handling:
Read the ORER flag in SCLSR to
identify any error, perform the
appropriate error handling, then clear
the ORER flag to 0. Reception cannot
be resumed while the ORER flag is
set to 1.
16.3.1 I²C Bus Control Register 1 795
(ICCR1)
16.3.2 I²C Bus Control Register 2 799
(ICCR2)
16.3.3 I²C Bus Mode Register
801
(ICMR)
Description of bit 7 amended.
0: This module is halted. (SCL and SDA pins function
as ports.)
Description of bit 1 amended.
Resets bits BC[2:0] in ICMR and IIC3 internal circuits. If
this bit is set to 1 when hang-up occurs because of
communication failure during I²C bus operation, bits
BC[2:0] in ICMR and IIC3 internal circuits can be reset.
Description of bits 2 to 0 amended.
… The value returns to B'000 at the end of a data
transfer, including the acknowledge bit. And the value
becomes B'111 automatically after the stop condition
detection. These bits are cleared by a power-on reset
and in software standby mode and module standby
mode. …
Rev. 3.00 Jun. 18, 2008 Page 1146 of 1160
REJ09B0191-0300