SH7206 Datasheet, PDF (168/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Interrupt Controller (INTC)
Number of States
Item
Peripheral
NMI
User Break H-UDI
IRQ, PINT Module
Remarks
Interrupt
No register Min.
response time banking
5 Icyc +
2 Bcyc +
1 Pcyc +
m1 + m2
6 Icyc +
m1 + m2
5 Icyc +
1 Pcyc +
m1 + m2
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
200-MHz operation*¹*²:
0.040 to 0.110 µs
Max.
6 Icyc +
2 Bcyc +
1 Pcyc +
2(m1 + m2) +
m3
7 Icyc +
2(m1 + m2) +
m3
6 Icyc +
1 Pcyc +
2(m1 + m2) +
m3
6 Icyc +
3 Bcyc +
1 Pcyc +
2(m1 + m2) +
m3
6 Icyc +
1 Bcyc +
1 Pcyc +
2(m1 + m2) +
m3
200-MHz operation*¹*²:
0.060 to 0.130 µs
Register Min. 

5 Icyc +
5 Icyc +
5 Icyc +
200-MHz operation*¹*²:
banking
1 Pcyc +
3 Bcyc +
1 Bcyc +
0.040 to 0.110 µs
without
m1 + m2
1 Pcyc +
1 Pcyc +
register
m1 + m2
m1 + m2
bank
Max. 

14 Icyc +
14 Icyc +
14 Icyc +
200-MHz operation*¹*²:
overflow
1 Pcyc +
3 Bcyc +
1 Bcyc +
0.085 to 0.155 µs
m1 + m2
1 Pcyc +
1 Pcyc +
m1 + m2
m1 + m2
Register Min. 

5 Icyc +
5 Icyc +
5 Icyc +
200-MHz operation*¹*²:
banking
1 Pcyc +
3 Bcyc +
1 Bcyc +
0.040 to 0.110 µs
with
m1 + m2
1 Pcyc +
1 Pcyc +
register
m1 + m2
m1 + m2
bank
Max. 

5 Icyc +
5 Icyc +
5 Icyc +
200-MHz operation*¹*²:
overflow
1 Pcyc + m1 + 3 Bcyc +
1 Bcyc +
0.135 to 0.205 µs
m2 + 19(m4) 1 Pcyc + m1 + 1 Pcyc + m1 +
m2 + 19(m4) m2 + 19(m4)
Notes: m1 to m4 are the number of states needed for the following memory accesses.
m1: Vector address read (longword read)
m2: SR save (longword write)
m3: PC save (longword write)
m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the
stack.
1. In the case that m1 = m2 = m3 = m4 = 1 Icyc.
2. In the case that (Iφ, Bφ, Pφ) = (200 MHz, 66 MHz, 33 MHz).
Rev. 3.00 Jun. 18, 2008 Page 144 of 1160
REJ09B0191-0300