SH7206 Datasheet, PDF (828/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 I²C Bus Interface 3 (IIC3)
16.3.5 I²C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status.
ICSR is initialized to H'00 by a power-on reset.
Bit: 7
6
5
4
3
2
1
TDRE TEND RDRF NACKF STOP AL/OVE AAS
Initial value: 0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W
0
ADZ
0
R/W
Initial
Bit
Bit Name Value R/W Description
7
TDRE
0
R/W Transmit Data Register Empty
[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When data is written to ICDRT
[Setting conditions]
• When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
• When TRS is set
• When the start condition (including retransmission)
is issued
• When slave mode is changed from receive mode to
transmit mode
6
TEND
0
R/W Transmit End
[Clearing conditions]
• When 0 is written in TEND after reading TEND = 1
• When data is written to ICDRT
[Setting conditions]
• When the ninth clock of SCL rises with the I²C bus
format while the TDRE flag is 1
• When the final bit of transmit frame is sent with the
clocked synchronous serial format
Rev. 3.00 Jun. 18, 2008 Page 804 of 1160
REJ09B0191-0300