SH7206 Datasheet, PDF (700/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Port Output Enable 2 (POE2)
Initial
Bit Bit Name Value R/W Description
5, 4 POE2M[1:0] 00
R/W*² POE2 Mode
These bits select the input mode of the POE2 pin.
00: Accept request on falling edge of POE2 input
01: Accept request when POE2 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE2 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE2 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
3, 2 POE1M[1:0] 00
R/W*² POE1 Mode
These bits select the input mode of the POE1 pin.
00: Accept request on falling edge of POE1 input
01: Accept request when POE1 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE1 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE1 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
1, 0 POE0M[1:0] 00
R/W*² POE0 Mode
These bits select the input mode of the POE0 pin.
00: Accept request on falling edge of POE0 input
01: Accept request when POE0 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE0 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE0 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
Rev. 3.00 Jun. 18, 2008 Page 676 of 1160
REJ09B0191-0300