SH7206 Datasheet, PDF (175/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Interrupt Controller (INTC)
Figure 5.12 shows the timing for saving to a register bank. Saving to a register bank takes place
between the start of interrupt exception handling and the start of fetching the first instruction in the
interrupt exception service routine.
3 Icyc + m1 + m2
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc
m1 m2 m3
IRQ
Instruction (instruction replacing
interrupt exception handling)
Overrun fetch
F D E EMMME
(1) VTO, PR, GBR, MACL
(2) R12, R13, R14, MACH
(3) R8, R9, R10, R11
Saved to bank
F
(4) R4, R5, R6, R7
(5) R0, R1, R2, R3
First instruction in interrupt exception
service routine
FDE
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Figure 5.12 Bank Save Timing
(2) Restoration from Bank
The RESBANK (restore from register bank) instruction is used to restore data saved in a register
bank. After restoring data from the register banks with the RESBANK instruction at the end of the
interrupt exception service routine, execute the RTE instruction to return from interrupt exception
service routine.
Rev. 3.00 Jun. 18, 2008 Page 151 of 1160
REJ09B0191-0300