SH7206 Datasheet, PDF (260/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
• CS4WCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
BST[1:0]
-
-
BW[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R
R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
SW[1:0]
W[3:0]
WM
-
-
-
-
HW[1:0]
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R
R
R
R R/W R/W
Bit
Bit Name
31 to 22 
21, 20 BST[1:0]
Initial
Value
All 0
00
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Burst Count Specification
Specify the burst count for 16-byte access. These bits
must not be set to B'11.
Bus Width BST[1:0] Burst count
8 bits
00
16 burst × one time
01
4 burst × four times
16 bits
00
8 burst × one time
01
2 burst × four times
10
4-4 or 2-4-2 burst
32 bits
xx
4 burst × one time
19, 18 
17, 16 BW[1:0]
All 0
00
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted
between the second or subsequent access cycles in
burst access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
Rev. 3.00 Jun. 18, 2008 Page 236 of 1160
REJ09B0191-0300