SH7206 Datasheet, PDF (429/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Figure 9.17 shows the TEND output timing.
Section 9 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
DACK
DMAC
End of DMA transfer
CPU
DMAC
CPU
CPU
TEND
Figure 9.17 Example of DMA Transfer End Signal Timing
(Cycle Steal Mode Level Detection)
The unit of the DMA transfer is divided into multiple bus cycles when 16-byte transfer is
performed for an 8-bit, 16-bit, or 32-bit external device, when longword access is performed for an
8-bit or 16-bit external device, or when word access is performed for an 8-bit external device.
When a setting is made so that the DMA transfer size is divided into multiple bus cycles and the
CS signal is negated between bus cycles, note that DACK and TEND are divided like the CS
signal for data alignment as shown in figure 9.18. Also, the DREQ sampling may not be detected
correctly with divided DACK, and one extra overrun may occur at maximum. Use a setting that
does not divide DACK or specify a transfer size smaller than the external device bus width if
DACK is divided.
Rev. 3.00 Jun. 18, 2008 Page 405 of 1160
REJ09B0191-0300