SH7206 Datasheet, PDF (456/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
• TIORL_0, TIORL_3, TIORL_4
Bit: 7
Initial value: 0
R/W: R/W
6
5
IOD[3:0]
0
0
R/W R/W
4
0
R/W
3
0
R/W
2
1
IOC[3:0]
0
0
R/W R/W
0
0
R/W
Bit
Bit Name
7 to 4 IOD[3:0]
3 to 0 IOC[3:0]
Initial
Value
0000
0000
R/W
R/W
R/W
Description
I/O Control D0 to D3
Specify the function of TGRD.
See the following tables.
TIORL_0: Table 10.13
TIORL_3: Table 10.17
TIORL_4: Table 10.19
I/O Control C0 to C3
Specify the function of TGRC.
See the following tables.
TIORL_0: Table 10.21
TIORL_3: Table 10.25
TIORL_4: Table 10.27
• TIORU_5, TIORV_5, TIORW_5
Bit: 7
6
-
-
Initial value: 0
0
R/W: R R
5
4
3
2
1
0
-
IOC[4:0]
0
0
0
0
0
0
R R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7 to 5 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4 to 0 IOC[4:0] 00000 R/W I/O Control C0 to C4
Specify the function of TGRU_5, TGRV_5, and
TGRW_5.
For details, see table 10.28.
Rev. 3.00 Jun. 18, 2008 Page 432 of 1160
REJ09B0191-0300