SH7206 Datasheet, PDF (140/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Interrupt Controller (INTC)
Register Name
Interrupt priority
register 13
Interrupt priority
register 14
Bits 15 to 12
MTU5S
(TGI5U, TGI5V,
TGI5W)
SCIF0
Bits 11 to 8
POE2
(OEI3)
SCIF1
Bits 7 to 4
IIC3
SCIF2
Bits 3 to 0
Reserved
SCIF3
As shown in table 5.3, by setting the 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3
to 0) with values from H'0 (0000) to H'F (1111), the priority of each corresponding interrupt is set.
Setting of H'0 means priority level 0 (the lowest level) and H'F means priority level 15 (the
highest level).
IPR01, IPR02, and IPR05 to IPR14 are initialized to H'0000 by a power-on reset.
Rev. 3.00 Jun. 18, 2008 Page 116 of 1160
REJ09B0191-0300