SH7206 Datasheet, PDF (971/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 I/O Ports
20.2.1 Register Descriptions
Table 20.1 lists the port A registers.
Table 20.1 Register Configuration
Register Name
Abbreviation R/W
Port A data register H PADRH
R/W
Port A data register L PADRL
R/W
Port A port register H PAPRH
R
Port A port register L PAPRL
R
Initial Value
H'3C00
H'xx00
H'3xxx
H'xxxx
Address
H'FFFE3800
H'FFFE3802
H'FFFE381C
H'FFFE381E
Access Size
8, 16, 32
8, 16
8, 16, 32
8, 16
20.2.2 Port A Data Registers H, L (PADRH, PADRL)
PADRH and PADRL are 16-bit readable/writable registers that store port A data. Bits PA25DR to
PA16DR, PA13DR to PA11DR, and PA9DR to PA0DR correspond to pins
PA25/CE2B/DACK3/POE8/PINT7 to PA16/WE3/DQMUU/ICIOWR/AH/DREQ2/CKE,
PA13/WE1/DQMLU/WE/POE7 to PA11/CS1/POE5, and PA9/TCLKD/IRQ3/FRAME/CKE to
PA0/RxD0/PINT0/CS4, respectively.
When a pin function is general output, if a value is written to PADRH or PADRL, that value is
output directly from the pin, and if PADRH or PADRL is read, the register value is returned
directly regardless of the pin state.
When a pin function is general input, if PADRH or PADRL is read, the pin state, not the register
value, is returned directly. If a value is written to PADRH or PADRL, although that value is
written into PADRH or PADRL, it does not affect the pin state. Table 20.2 summarizes PADRH
and PADRL read/write operations.
PADRH and PADRL are initialized to the respective values shown in table 20.1 by a power-on
reset. PADRH and PADRL are not initialized by a manual reset or in sleep mode or software
standby mode.
Rev. 3.00 Jun. 18, 2008 Page 947 of 1160
REJ09B0191-0300