SH7206 Datasheet, PDF (729/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 13 Compare Match Timer (CMT)
13.3 Operation
13.3.1 Interval Count Operation
When an internal clock is selected with the CKS[1:0] bits in CMCSR and the STR bit in CMSTR
is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and
CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the
CMIE bit in CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested.
CMCNT then starts counting up again from H'0000.
Figure 13.2 shows the operation of the compare match counter.
CMCNT value
CMCOR
Counter cleared by compare
match with CMCOR
H'0000
Time
Figure 13.2 Counter Operation
13.3.2 CMCNT Count Timing
One of four clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the peripheral clock
(Pφ) can be selected with the CKS[1:0] bits in CMCSR. Figure 13.3 shows the timing.
Peripheral clock
(Pφ)
Internal clock
Count clock ^Clock
N
CMCNT
Clock
N+1
N
N+1
Figure 13.3 Count Timing
Rev. 3.00 Jun. 18, 2008 Page 705 of 1160
REJ09B0191-0300