SH7206 Datasheet, PDF (1178/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Clock operating modes ............................. 74
Clock pulse generator (CPG).................... 69
Clock timing ......................................... 1074
Clocked synchronous serial format ........ 820
CMCNT count timing............................. 705
Coherency of cache and external
memory................................................... 193
Compare match timer (CMT) ................. 699
Complementary PWM mode .................. 534
Conditions for determining number of
idle cycles ............................................... 344
Conflict between byte-write and
count-up processes of CMCNT .............. 710
Conflict between word-write and
count-up processes of CMCNT .............. 709
Conflict between write and
compare-match processes of CMCNT.... 708
Control signal timing ............................ 1077
CPU .......................................................... 29
Crystal oscillator....................................... 71
CSn assert period expansion................... 274
Cycle steal mode..................................... 398
D
D/A converter (DAC) ............................. 863
D/A converter characteristics ............... 1127
D/A output hold function in software
standby mode.......................................... 869
Data array ....................................... 180, 195
Data array read ....................................... 195
Data array write ...................................... 195
Data format in registers ............................ 34
Data formats in memory ........................... 34
Data transfer instructions.......................... 54
Data transfer with interrupt request
signals..................................................... 154
DC characteristics................................. 1069
Dead time compensation ........................ 590
Deep power-down mode......................... 322
Rev. 3.00 Jun. 18, 2008 Page 1154 of 1160
REJ09B0191-0300
Definitions of A/D conversion
accuracy .................................................. 857
Delayed branch instructions...................... 37
Direct memory access controller
(DMAC).................................................. 357
Displacement accessing ............................ 39
Divider 1 ................................................... 71
Divider 2 ................................................... 71
DMA transfer flowchart.......................... 386
DMAC activation.................................... 596
DMAC module timing .......................... 1115
DREQ pin sampling timing .................... 403
Dual address mode.................................. 395
E
Effective address calculation .................... 40
Electrical characteristics ....................... 1067
Endian ..................................................... 264
Equation for getting SCBRR value......... 749
Exception handling ................................... 87
Exception handling state ........................... 68
Exception handling vector table................ 91
Exception source generation
immediately after delayed branch
instruction ............................................... 106
Exceptions triggered by instructions....... 103
External pulse width measurement ......... 589
External request mode............................. 387
External trigger input timing................... 855
F
Fixed mode ............................................. 391
Full-scale error........................................ 857
G
General illegal instructions ..................... 104
General registers ....................................... 29