SH7206 Datasheet, PDF (745/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 14 Watchdog Timer (WDT)
14.4.2 Changing the Frequency
To change the frequency used by the PLL, use the WDT. When changing the frequency only by
switching the divider, do not use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the
counter in WTCNT. These values should ensure that the time till count overflow is longer than
the clock oscillation settling time. However, the WDT counts up using the clock after the
setting.
3. When the frequency control register (FRQCR) is written to, this LSI stops temporarily. The
WDT starts counting.
4. When the WDT count overflows, the CPG resumes supplying the clock and this LSI resumes
operation. The WOVF flag in WRCSR is not set when this happens.
5. The counter stops at the value of H'00.
6. Before changing WTCNT after execution of the frequency change instruction, always confirm
that the value of WTCNT is H'00 by reading from WTCNT.
Rev. 3.00 Jun. 18, 2008 Page 721 of 1160
REJ09B0191-0300