SH7206 Datasheet, PDF (72/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 2 CPU
Instruction Formats
i format
15
0
xxxx xxxx iiii iiii
ni format
15
0
xxxx nnnn iiii iiii
ni3 format
15
0
xxxx xxxx nnnn x iii
Source
Operand
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
Destination
Operand
Example
Indexed GBR
indirect
AND.B
#imm,@(R0,GBR)
R0 (Register direct) AND #imm,R0
—
TRAPA #imm
nnnn: Register direct ADD #imm,Rn
nnnn: Register direct —
BLD
iii: Immediate
—
nnnn: Register direct BST
iii: Immediate
#imm3,Rn
#imm3,Rn
ni20 format
32
16
xxxx nnnn iiii xxxx
iiiiiiiiiiiiiiiiiiii:
Immediate
nnnn: Register direct MOVI20
#imm20, Rn
15
0
iiii iiii iiii iiii
nid format
32
16
xxxx nnnn xiii xxxx
nnnndddddddddddd: —
Register indirect with
displacement
BLD.B
#imm3,@(disp12,Rn
)
15
0
xxxx dddd dddd dddd
iii: Immediate
—
nnnndddddddddddd: BST.B
Register indirect with #imm3,@(disp12,Rn
displacement
)
iii: Immediate
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
Rev. 3.00 Jun. 18, 2008 Page 48 of 1160
REJ09B0191-0300