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| SH7641 Datasheet, PDF (996/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series | |||
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Section 25 Electrical Characteristics
CKIO
A25 to A0
A12/A11*1
CSn
RD/WR
Tr
Tc1
Tc2
Tc3
Tc4
tAD1
tAD1
Row
address
tAD1
tAD1
tCSD1
tAD1
tAD1
Column
address
tAD1
Write command
tAD1
tAD1
tCSD1
tRWD1
tRWD1
tRWD1
RASU/L
CASU/L
DQMxx
D31 to D0
BS
tRASD1
tRASD1
tCASD1
tDQMD1
tWDD2
tWDH2
tBSD
tCASD1
tDQMD1
tWDD2
tWDH2
tBSD
CKE
DACKn*2
tDACD
(High)
tDACD
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Figure 25.34 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle, TRWL = 0 Cycle)
Rev. 4.00 Sep. 14, 2005 Page 946 of 982
REJ09B0023-0400
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