SH7641 Datasheet, PDF (175/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 3 DSP Operation
#imm is 8 bits while RC is 12 bits. Therefore, to set more than 256 into RC, use Rm. A sample
program is shown below.
LDRS RptStart;
LDRE RptEnd3+4;
SETRC #imm;
RC = #imm
instr0;
; instr1–5 executes repeatedly
RptStart: instr1;
RptEnd3:
instr2;
instr3;
instr4;
RptEnd:
instr5;
instr6;
In this implementation, there are some restrictions to use this repeat control function as follows:
1. There must be at least one instruction between SETRC and the first instruction in a repeat
loop.
2. LDRS and LDRE must be executed before SETRC.
3. In a case that the repeat loop has four or more instructions in it, stall cycles are necessary
according to the pipeline state at execution.
4. If a repeat loop has less than four instructions in it, it cannot have any branch instructions
(BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR and JMP), repeat control
instructions (SETRC, LDRS and LDRE), load instructions for SR, RS, RE, and a TRAPA
instruction in it. If these instructions are executed, a general invalid instruction exception
handling starts, and a certain address value shown in table 3.15 is stored into SPC.
Table 3.15 Address Value to be Stored into SPC (1)
Condition
RC ≥ 2
RC = 1
Location
Any
Any
Address to be Pushed
RptStart
Address of the illegal instruction
Rev. 4.00 Sep. 14, 2005 Page 125 of 982
REJ09B0023-0400