SH7641 Datasheet, PDF (229/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 7 Cache
Section 7 Cache
7.1 Features
The cache specifications are listed in table 7.1.
Table 7.1 Cache Specifications
Parameter
Capacity
Structure
Locking
Line size
Number of entries
Write system
Replacement method
Specification
16 kbytes
Instructions/data mixed, 4-way set associative
Way 2 and way 3 are lockable
16 bytes
256 entries/way
P0, P1, P3: Write-back/write-through selectable
Least-recently-used (LRU) algorithm
In this LSI, the address space is partitioned into five subdivisions, and the cache access method is
determined by the address. Table 7.2 shows the kind of cache access available in each address
space subdivision.
Table 7.2 Address Space Subdivisions and Cache Operation
Address Bits
A31 to 29
0xx
100
101
110
111
Address Space
Subdivision
P0
P1
P2
P3
P4
Cache Operation
Write-back/write-through selectable
Write-back/write-through selectable
Non-cacheable
Write-back/write-through selectable
I/O area, non-cacheable
Note that area P4 is an I/O area, to which the addresses of on-chip registers, etc., are allocated.
To ensure data consistency, the cache stores 32-bit addresses with the upper 3 bits masked to 0.
Rev. 4.00 Sep. 14, 2005 Page 179 of 982
REJ09B0023-0400