SH7641 Datasheet, PDF (124/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Instruction
DMULU.L Rm,Rn
Instruction Code
0011nnnnmmmm0101
DT
Rn
0100nnnn00010000
EXTS.B Rm,Rn
0110nnnnmmmm1110
EXTS.W Rm,Rn
0110nnnnmmmm1111
EXTU.B Rm,Rn
0110nnnnmmmm1100
EXTU.W Rm,Rn
0110nnnnmmmm1101
MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
MUL.L Rm,Rn
MULS.W Rm,Rn
0000nnnnmmmm0111
0010nnnnmmmm1111
MULU.W Rm,Rn
0010nnnnmmmm1110
NEG
NEGC
Rm,Rn
Rm,Rn
SUB
SUBC
Rm,Rn
Rm,Rn
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
Operation
Execution
States
T Bit
Unsigned operation of
Rn × Rm → MACH,
MACL 32 × 32 → 4 bits
2(5) *¹
—
Rn – 1 → Rn, if Rn = 0, 1
1
→ T, else 0 → T
Comparison
result
A byte in Rm is sign-extended 1
—
→ Rn
A word in Rm is sign-extended 1
—
→ Rn
A byte in Rm is zero-extended 1
—
→ Rn
A word in Rm is zero-extended 1
—
→ Rn
Signed operation of (Rn)
2(5)*¹
—
× (Rm) → MAC → MAC,
Rn + 4 → Rn, Rm + 4 → Rm
32 × 32 + 64 → 64 bits
Signed operation of (Rn)
2(5)*¹
—
× (Rm) → MAC → MAC,
Rn + 2 → Rn, Rm + 2 → Rm
16 × 16 + 64 → 64 bits
Rn × Rm → MACL
32 × 32 → 32 bits
2(5)*¹
—
Signed operation of
Rn × Rm → MAC
16 × 16 → 32 bits
1(3)*²
—
Unsigned operation of
Rn × Rm → MAC
16 × 16 → 32 bits
1(3)*²
—
0–Rm → Rn
1
—
0–Rm–T → Rn,
Borrow → T
1
Borrow
Rn–Rm → Rn
1
—
Rn–Rm–T → Rn,
Borrow → T
1
Borrow
Rev. 4.00 Sep. 14, 2005 Page 74 of 982
REJ09B0023-0400