SH7641 Datasheet, PDF (356/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
1
HW1
0
R/W Delay Cycles from RD, WEn Negation to Address, CSn
0
HW0
0
R/W ^Negation
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
SDRAM*:
• CS2WCR
Bit
Bit Name
31 to 11 
Initial
Value
All 0
10

1
9

0
8
A2CL1
1
7
A2CL0
0
6 to 0

All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Reserved
This bit is always read as 1. The write value should
always be 1.
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W CAS Latency for Area 2
R/W Specify the CAS latency for area 2.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 4.00 Sep. 14, 2005 Page 306 of 982
REJ09B0023-0400