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SH7641 Datasheet, PDF (137/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series
Section 2 CPU
The correspondence between DSP data transfer operands and registers is shown in table 2.28.
CPU core registers are used as a pointer address that indicates a memory address.
Table 2.28 Correspondence between DSP Data Transfer Operands and Registers
Register
Ax Ix
Dx Ay Iy
Dy Da As Ds
CPU
R0
registers R1


















R2 (As2) 






Yes 
R3 (As3) 






Yes 
R4 (Ax0) Yes 



—

Yes 
R5 (Ax1) Yes 



—

Yes 
R6 (Ay0) 


Yes 




R7 (Ay1) 


Yes 




R8 (Ix) 
Yes 






R9 (Iy) 
—


Yes 



DSP
A0
registers A1
—





Yes 
Yes
—





Yes 
Yes
M0


—
—




Yes
M1


—
—




Yes
X0


Yes 




Yes
X1


Yes 




Yes
Y0





Yes 

Yes
Y1





Yes 

Yes
A0G








Yes
A1G








Yes
Rev. 4.00 Sep. 14, 2005 Page 87 of 982
REJ09B0023-0400