SH7641 Datasheet, PDF (257/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 9 Exception Handling
Illegal general instruction exception:
• Conditions
 When undefined code not in a delay slot is decoded
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Note: For details on undefined code, refer to SH-3/SH-3E/SH-3DSP Software Manual. When an
undefined code other than H'FC00 to H'FFFF is decoded, operation cannot be guaranteed.
• Types
Instruction synchronous, re-execution type
• Save address
An instruction address where an exception occurs
• Exception code
H'180
• Remarks
None
Illegal slot instruction:
• Conditions
 When undefined code in a delay slot is decoded
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
 When an instruction that rewrites PC in a delay slot is decoded
Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
• Types
Instruction synchronous, re-execution type
• Save address
A delayed branch instruction address
• Exception code
H'1A0
• Remarks
None
Rev. 4.00 Sep. 14, 2005 Page 207 of 982
REJ09B0023-0400