SH7641 Datasheet, PDF (727/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
Initial
Bit
Bit Name value R/W Description
11 to 9 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
8
PIE
0
R/W Port Interrupt Enable
This bit enables/disables interrupt requests when any
of the POE0F to POE3F bits of the ICSR1 are set to 1
0: Interrupt requests disabled
1: Interrupt requests enabled
7
POE3M1 0
R/W POE3 mode 1, 0
6
POE3M0 0
R/W These bits select the input mode of the POE3 pin.
00: Accept request on falling edge of POE3 input
01: Accept request when POE3 input has been
sampled for 16 Pφ/8 clock pulses, and all are low
level.
10: Accept request when POE3 input has been
sampled for 16 Pφ/16 clock pulses, and all are
low level.
11: Accept request when POE3 input has been
sampled for 16 Pφ/128 clock pulses, and all are
low level.
5
POE2M1 0
R/W POE2 mode 1, 0
4
POE2M0 0
R/W These bits select the input mode of the POE2 pin.
00: Accept request on falling edge of POE2 input
01: Accept request when POE2 input has been
sampled for 16 Pφ/8 clock pulses, and all are low
level.
10: Accept request when POE2 input has been
sampled for 16 Pφ/16 clock pulses, and all are
low level.
11: Accept request when POE2 input has been
sampled for 16 Pφ/128 clock pulses, and all are
low level.
Rev. 4.00 Sep. 14, 2005 Page 677 of 982
REJ09B0023-0400