SH7641 Datasheet, PDF (364/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
12.4.4 SDRAM Control Register (SDCR)
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
This register is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual
reset and in the standby mode.
Bit
Bit Name
31 to 21 
20
A2ROW1
19
A2ROW0
18

17
A2COL1
16
A2COL0
15, 14 
Initial
Value
All 0
0
0
0
0
0
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Bits of Row Address for Area 2
R/W Specify the number of bits of row address for area 2.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (Setting prohibited)
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Number of Bits of Column Address for Area 2
R/W Specify the number of bits of column address for
area 2.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (Setting prohibited)
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 4.00 Sep. 14, 2005 Page 314 of 982
REJ09B0023-0400