SH7641 Datasheet, PDF (347/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Bit
5 to 2
1
0
Bit Name

HW1
HW0
Initial
Value
All 0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Delay Cycles from RD, WEn Negation to Address,
R/W ^{CSn Negation}
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS6AWCR
Bit
Bit Name
31 to 13 
12
SW1
11
SW0
Initial
Value
All 0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Delay Cycles from Address, CSn Assertion
R/W ^{to RD, WE Assertion}
Specify the number of delay cycles from address and
CSn assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 4.00 Sep. 14, 2005 Page 297 of 982
REJ09B0023-0400