SH7641 Datasheet, PDF (243/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 8 X/Y Memory
Section 8 X/Y Memory
This LSI has on-chip X-RAM and Y-RAM. It can be used by CPU, DSP and DMAC to store
instructions or data.
8.1 Features
The X/Y Memory features are listed in table 8.1.
Table 8.1 X/Y Memory Specifications
Parameter
Features
Addressing method Mapping is possible in space P0 or P2
Ports
3 independent read/write ports
• 8-/16-/32-bit access by the CPU (via L bus or I bus)
• Maximum of two simultaneous 16-bit accesses (via X and Y buses), or
16/32-bit accesses, by the DSP (via L bus)
• 8-/16-/32-bit access by the DMAC (via I bus)
Size
8-kbyte RAM for X and Y memory each
The X memory resides in addresses H'05007000 to H'05008FFF in space P0 or addresses
H'A5007000 to H'A5008FFF (8 kbytes) in space P2. The X RAM is divided into page 0 and page
1 according to the addresses. The X memory can be accessed from the L bus, X bus, and I bus.
The Y memory resides in addresses H'05017000 to H'05018FFF in space P0 or addresses
H'A5017000 to H'A5018FFF (8 kbytes) in space P2. The X RAM is divided into page 0 and page
1 according to the addresses. The Y memory can be accessed from the L bus, Y bus, and I bus.
In the event of simultaneous accesses to the same page from different buses, the priority order is: I
bus > X bus > L bus in the X memory and I bus > Y bus > L bus in the Y memory. Since this kind
of contention tends to lower X/Y memory accessibility, it is advisable to provide software
measures to prevent such contention as far as possible. For example, contention will not arise if
different memory or different pages are accessed by each bus.
X/Y memory is accessed by the CPU or DSP from space P0 via the I bus, a contention with the
DMAC may occur on the I bus. Since this kind of contention also tends to lower X/Y memory
accessibility, it is advisable to provide software measures to prevent such contention as far as
possible. For example, contention on the I bus can be prevented by using space P2 when the X/Y
memory is accessed by the CPU or DSP.
Rev. 4.00 Sep. 14, 2005 Page 193 of 982
REJ09B0023-0400