SH7641 Datasheet, PDF(263/1036 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SH7641 Datasheet, PDF (263/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

◁

Section 9 Exception Handling

Table 9.4 SPC Value When a Re-Execution Type Exception Occurs in Repeat Control

Instruction Where an

Exception Occurs

1

Number of Instructions in a Repeat Loop

2

3

4 or Greater

RptDtct

RptDtct

RptDtct

RptDtct

RptDtct

RptDtct1

RptDtct1

RptDtct1

RptDtct1

RptDtct1

RptDtct2

ï£§

RptDtct1

RptDtct1

RS-4

RptDtct3

ï£§

ï£§

RptDtct1

RS-2

Note:

The following labels are used here.

RptDtct: Repeat detection instruction address

RptDtct1: An instruction address one instruction following the repeat detection instruction

RptDtct2: An instruction address two instruction following the repeat detection instruction

RptDtct3: An instruction address three instruction following the repeat detection instruction

RS:

Repeat start instruction address

If a re-execution type exception is accepted at an instruction in the hatched areas above, a

return address to be saved in the SPC is incorrect. If SR.RC[11:0] is 1 or 0, a correct return

address is saved in the SPC.

Illegal Instruction Exception in Repeat Control Period: If one of the following instructions is

executed at the address following RptDtct1, a general illegal instruction exception occurs. For

details on an address to be saved in the SPC, refer to SPC Saved by an Exception in Repeat

Control Period description in section 9.4.2, Exception in Repeat Control Period.

â¢ Branch instructions

BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA

â¢ Repeat control instructions

SETRC, LDRS, LDRE

â¢ Load instructions for SR, RS, and RE

LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+, Rs

Note:

In a repeat loop consisting of one to three instructions, some restrictions apply to repeat

detection instructions and all the remaining instructions. In a repeat loop consisting of four

or more instructions, restrictions apply to only the three instructions that include a repeat

end instruction.

Rev. 4.00 Sep. 14, 2005 Page 213 of 982

REJ09B0023-0400

▷