SH7641 Datasheet, PDF (241/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 7 Cache
Data Array Read: The data specified by L (bits 3 and 2) in the address is read from the entry
address specified by the address and the entry corresponding to the way.
Data Array Write: The longword data specified by the data is written to the position specified by
L (bits 3 and 2) in the address from the entry address specified by the address and the entry
corresponding to the way.
1. Address array access
(a) Address specification
Read access
31
24 23
14 13 12 11
4
1111 0000
*^{…………}*
W
Entry
Write access
31
24 23
14 13 12 11
4
1111 0000
*^{…………}*
W
Entry
(b) Data specification (both read and write accesses)
31 30 29
000
Address tag (28 to 10)
10 9
4
LRU
32
0
0000
32
0
A 000
32
XX
10
UV
2. Data array access (both read and write accesses)
(a) Address specification
31
24
1111 0001
23
14
*^{…………}*
13 12
W
11
Entry
4
3
21
0
L
00
(b) Data specification
31
0
Longword
[Legend]
*: Don't care bit
X: 0 for read, don't care for write
Figure 7.4 Specifying Address and Data for Memory-Mapped Cache Access
Rev. 4.00 Sep. 14, 2005 Page 191 of 982
REJ09B0023-0400