SH7641 Datasheet, PDF (420/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Power-down Tnop
Tr
CKIO
Tc1
Td1
Tde
Tap Power-down
CKE
A25 to A0
A12/A11*¹
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.32 Power-Down Mode Access Timing
The conditions to shift to the power-down mode are as follows.
• Write or read access (including instruction fetch) occurs to the memory other than the
SDRAM, which is to be set to the power-down mode.
• Read or write access occurs to the control register with the address H'Axxx xxxx or to the
peripheral I/O register.
Rev. 4.00 Sep. 14, 2005 Page 370 of 982
REJ09B0023-0400